1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection technology, more specifically, to an ESD protection circuit with whole-chip ESD protection, in which an ESD event can simultaneously conduct a plurality of discharge paths and the ESD current automatically leads to that with the lowest resistance to ground, preventing the ESD current from flowing into the internal circuit due to layout or the position shift of ESD devices caused by the manufacturing process.
2. Description of the Related Art
ESD phenomena have become a reliability issue in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) because of technology scaling and high frequency requirements. ESD events happen in various steps of the semiconductor process, such as manufacturing, packaging, shipping and assembly, and may cause damage to the semiconductor chips. Current ESD protection technology utilizes ESD protection circuits or devices close to input/output pads or internally within chips to reduce the possibility of ESD damage. There are four possible ESD-stress modes, described as follows:
(1) Positive-to-VSS (or PS) mode: ESD stress at a pad with positive voltage polarity with respect to the grounded VSS line when the VDD line and other input/output pads are floating;
(2) Negative-to-VSS (or NS) mode: ESD stress at a pad with negative voltage polarity with respect to the grounded VSS line when the VDD line and other input/output pads are floating;
(3) Positive-to-VDD (or PD) mode: ESD stress at a pad with positive voltage polarity with respect to the grounded VDD line when the VSS line and other input/output pads are floating; and
(4) Negative-to-VDD (or ND) mode: ESD stress at a pad with negative voltage polarity with respect to the grounded VDD line when the VSS line and other input/output pads are floating.
The ESD protection circuit is designed to upgrade the immunity of semiconductor chips against these ESD stress modes. Several ESD protection circuits have been proposed and two MOS (Metal-Oxide-Semiconductor)-based ESD protection circuits are illustrated in the following description. One is an ESD protection circuit using gate-driven technique and another is an ESD protection circuit using substrate-triggering technique.
FIG. 1 (Prior Art) is a circuit diagram of a conventional ESD protection circuit using gate-driven technique. As shown in FIG. 1, the ESD protection circuit connected between input/output pad 100 and the VSS line includes an ESD detection circuit 200 and an NMOS transistor 300. NMOS transistor 300 is operated as an ESD protection device providing a discharge path. During normal operation, ESD detection circuit 200 does not output a bias voltage to the gate electrode of NMOS transistor 300 and NMOS transistor 300 is always turned off. When a PS-mode ESD event occurs at input/output pad 100, ESD detection circuit 200 outputs a bias voltage to the gate electrode of NMOS transistor 300 and drives the NMOS transistor 300 to enter snapback mode early to bypass the ESD current.
U.S. Pat. No. 5,717,560 and U.S. Pat. No. 5,910,874 illustrate two examples of the ESD protection circuits using gate-driven technique. In '560 patent, the ESD protection circuit has an NMOS transistor serving as an ESD protection device, which has a gate electrode connected to input/output pads. When an ESD event occurs, an ESD voltage is coupled to the gate electrode of the ESD protection device via coupling capacitance between the input/output pads and the VDD/VSS lines, thus turning on the ESD protection device to conduct ESD current. In '874 patent, the ESD protection circuit employs an inverter as an ESD detection circuit. When an ESD event occurs, it outputs a bias voltage for conducting the ESD protection device to bypass the ESD current.
FIG. 2 (Prior Art) is a circuit diagram of a conventional ESD protection circuit using substrate-triggering technique. The ESD protection circuit is also connected between input/output pad 110 and the VSS line, and comprises an ESD detection circuit 210 and an NMOS transistor 310. NMOS transistor 310 is operated as an ESD protection device providing a discharge path. The difference between the substrate-triggering scheme and the gate-driven scheme described above is the ESD detection circuit 210's utilization of a substrate-triggering current Ib to trigger the ESD protection device. During normal operation, ESD detection circuit 210 does not output the substrate-triggering current Ib to the substrate of NMOS transistor 310 and NMOS transistor 310 is, therefore, turned off. As a PS-mode ESD event occurs at input/output pad 110, ESD detection circuit 210 outputs the substrate-triggering current Ib to the substrate of NMOS transistor 310 and turns on a lateral npn bipolar junction transistor (BJT) of NMOS transistor 310 to enter snapback mode early to bypass the ESD current.
U.S. Pat. No. 5,744,842 and U.S. Pat. No. 6,072,219 illustrate two examples of the ESD protection circuits using substrate-triggering technique. In '842 patent, the ESD detection circuit is composed of an inverter, a resistor and a capacitor. In addition, the time constant of the RC circuit is designed to be substantially of the μs order to discriminate power-on events, which are substantially of the ms order, from ESD events, which are substantially of the ns order. Thus, the substrate-triggering current can be properly outputted to turn on field oxide devices (FODs) of ESD protection devices. During normal operation, the ESD detection circuit does not output the substrate-triggering current. When an ESD event occurs in the VDD line, the ESD detection circuit outputs the substrate-triggering current to the substrate of the FOD and triggers the parasitic npn BJT of the FOD to bypass ESD current. In '219 patent, the ESD protection circuit includes an ESD protection device and an ESD detection circuit, each of which consists of an NMOS transistor and a PMOS transistor. The transistors of the ESD detection circuit have lower trigger-on voltage and thus enter snapback mode early to introduce the substrate-triggering current into the substrate of the ESD protection circuit. Consequently, the parasitic BJT of the ESD protection device quickly turns on to bypass ESD current, thereby achieving ESD protection.
Conventional ESD protection circuits using gate-driven or substrate-triggering technique can effectively protect internal circuitry of the IC from ESD damage. In these conventional proposals, the ESD current is usually bypassed by a single discharge path, including one or more ESD protection devices. The conventional ESD protection scheme may not, however, work if the resistance of this single discharge path to ground is higher than that of the internal circuitry due to layout or the position shift of ESD devices caused by the manufacturing process since the ESD current always flows into the ground via the path having the lowest resistance to ground.